1. Field of the Invention
This invention relates to integrated circuit semiconductor devices, and more particularly to a method for fabricating dynamic random access memory (DRAM) devices having two-step contacts to word lines, commonly referred to as word-line strapping. This new two-step contact process replaces a single-step high-aspect-ratio contact opening, which is difficult to fabricate in high-density circuits as lateral dimensions on integrated circuits continue to decrease, and more specifically for word-line contacts on DRAMs.
2. Description of the Prior Art
As integrated circuit density increases, it becomes increasing difficult to manufacture ultra large scale integrated (ULSI) circuits. One of the problems associated with making these dense circuits is the increase in the number of material layers that requires etching high-aspect-ratio features in these underlying layers. One area of concern is the multilevel contact openings that must be etched to wire up the semiconductor devices on an integrated circuit. One area where this is of particular concern is the word-line strapping used to electrically connect the word lines in the memory cells to other parts of the circuit, such as the peripheral circuits on the DRAM chip. A stacked capacitor DRAM device in which the capacitor is formed over the device area results in several insulating layers having a cumulative thick insulating layer. Because of the thermal considerations, it is desirable to form the word-line metal contacts after forming the capacitors by high-temperature processing. Unfortunately, as the lateral dimensions decrease, it becomes increasingly difficult to etch small contact openings with high aspect ratios in the cumulatively thick insulating layer to the word line for word-line strapping. To etch high-aspect-ratio contacts, it is necessary to use a relatively thick photoresist as an etch mask, which is difficult to expose and develop with high resolution.
Several methods of making electrical contacts on integrated circuits, including DRAM circuits, have been described in the prior art. For example, Yoon et al. U.S. Pat. No. 5,620,917, teach a method for making a semiconductor memory device having a capacitor and contacts to the peripheral circuit regions without affecting the step difference between the memory cell and the peripheral circuit region when the storage electrodes are made thicker. Kim, U.S. Pat. No. 5,565,372, teaches a method for making self-aligned bit-line contacts to a semiconductor device in which a conductive layer is formed between the word line and bit line to minimize capacitor coupling between the word line and bit line. In U.S. Pat. No. 5,792,680 Sung et al. describe a method of forming low-cost DRAM cells on a substrate that has twin (P and N) wells, which requires etching high-aspect-ratio contacts in a thick insulating layer to source/drain areas in the N-well area. Tigelaar et al., U.S. Pat. No. 4,811,076, teach a method for making devices with double capacitors in which a metal interconnect layer is formed to provide ohmic contacts to silicide, silicon, and titanium nitride while providing a top plate for the double capacitors. Kim et al., U.S. Pat. No. 5,683,938, teach a method for filling contact holes with metal by a two-step deposition. However, Kim et al. do not describe a method for making a two-step contact on a DRAM device that has stacked capacitors.
Therefore there is still a need in the semiconductor industry to form high-aspect-ratio contact openings having small sizes in multilevels of insulating layers for word-line strapping on DRAM devices.